Japanese Patent Application No. 2000-270442, filed Sep. 6, 2000, is hereby incorporated by reference in its entirety.
The present invention relates to a level shift circuit and a semiconductor device, such as a liquid crystal driver IC, which uses the level shift circuit.
The output of a level shift circuit is switched fast by changing an input signal to the gate of an N-type MOS transistor (hereinafter called xe2x80x9cNMOS transistorxe2x80x9d) connected to a P-type MOS transistor (hereinafter called xe2x80x9cPMOS transistorxe2x80x9d) from a low level to a high level while the PMOS transistor is on.
In the level shift circuit, therefore, the series-connected PMOS transistor and NMOS transistor are turned on at the same time.
To enable fast switching in the level shift circuit, the logic of the output terminal connected to the drain of the NMOS transistor should be switched to LOW from HIGH quickly under that situation.
To meet the necessity, the current drive capability of the PMOS transistor is lowered while the current drive capability of the NMOS transistor is increased.
A current i which flows between the source and drain of an MOS transistor is i=xcex2(VGSxe2x88x92Vth)2/2. The coefficient xcex2 is inversely proportional to the gate length of the transistor and proportional to the gate width. Therefore, it is normal to make the gate length longer in order to reduce the current drive capability of the PMOS transistor and to widen the gate width in order to increase the current drive capability of the NMOS transistor. This inevitably increases the occupation area of the level shift circuit.
A large number of level shift circuits of this type are provided in a semiconductor device. In case where the semiconductor device is a liquid crystal driver IC, for example, the total quantity of the level shift circuits needed merely to generate a liquid crystal drive potential is equal to the number of at least signal electrodes. Accordingly, there are demands of reducing the occupation area of each level shift circuit.
Accordingly, aspects of the present invention can provide a level shift circuit of which occupation area can be reduced while ensuring a fast switching operation.
Further aspects of the present invention can provide integrated semiconductor devices which incorporate a level shift circuit with a small occupation area and is therefore suitable for a display drive IC to drive a liquid crystal.
A level shift circuit according to first aspects of the present invention comprises first and second circuits connected in parallel between a first supply line supplying a first potential and a second supply line supplying a second potential lower in an absolute value than the first potential,
wherein each of the first and second circuits includes first and second transistors of a first conductivity type and a second conductivity type transistor connected in series between the first and second supply lines in order from a first-supply-line side,
wherein a gate of the first transistor of the first conductivity type in the first circuit is connected to a drain of the second conductivity type transistor in the second circuit,
wherein a gate of the first transistor of the first conductivity type in the second circuit is connected to a drain of the second conductivity type transistor in the first circuit,
wherein input potentials opposite to each other are applied to gates of the second conductivity type transistors in the first and second circuits respectively, and output potentials level-shifted from the input potentials are output from drains of the second conductivity type transistors in the first and second circuits respectively, and
wherein a third supply line supplying a third potential via a resistor between the first and second potentials is connected to a gate of the second transistor of the first conductivity type in each of the first and second circuits.
In a level shift circuit according to a second aspect of the present invention, the second transistor of the first conductivity type in each of the first and second circuits is depletion type and the gate of the second transistor of the first conductivity type in each of the first and second circuits is connected to the first supply line.